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CY7C1012AV33
512K x 24 Static RAM
Features
* High speed -- tAA = 8 ns * Low active power -- 1080 mW (max.) * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE0, CE1 and CE2 features * Available in non Pb-free 119 ball PBGA. power-down feature that significantly consumption when deselected. reduces power
Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0-A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. The 24 I/O pins (I/O0-I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. The CY7C1012AV33 is available in a standard 119-ball PBGA.
Functional Description
The CY7C1012AV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0-I/O7, while CE1 controls the data on I/O8-I/O15, and CE2 controls the data on the data pins I/O16-I/O23. This device has an automatic
Functional Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
512K x 24 ARRAY
SENSE AMPS
I/O0-I/O7 I/O8-I/O15 I/O16-I/O23
COLUMN DECODER
CONTROL LOGIC
CE0, CE1, CE2 WE OE
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -8 8 300 300 50 -10 10 275 275 50 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05254 Rev. *E
A10 A11 A 12 A 13 A 14 A15 A16 A17 A18
Commercial Industrial Commercial/Industrial
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY7C1012AV33
Pin Configurations[1, 2]
119 PBGA
Top View
1 A B C D E F G H J K L M N P R T U NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC
2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
3 A A CE1 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
4 A CE0 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 DNU I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC
Notes: 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application.
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CY7C1012AV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
-8 Parameter VOH VOL VIH VIL[3] IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VOUT < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, Commercial CE > VCC - 0.3V, /Industrial VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Commercial Industrial Test Conditions[4] VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 300 300 100 2.0 -0.3 -1 -1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 100 -10 Max. Unit V V V V A A mA mA mA
ISB2
50
50
mA
Capacitance[5]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 10 Unit pF pF
AC Test Loads and Waveforms[6]
50 OUTPUT Z0 = 50 VTH = 1.5V 30 pF* * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.3V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 R1 317
(a)
(b)
(c)
Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time. 5. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1012AV33
AC Switching Characteristics Over the Operating Range[7]
-8 Parameter Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[11, 12] Write Cycle Time CE1, CE2, and CE3 LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[9] High-Z[9] 6 8 6 6 0 0 6 5 0 3 5 7 10 7 7 0 0 7 5.5 0 3 5 ns ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1, CE2, and CE3 LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[9] OE HIGH to High-Z[9] Low-Z[9] 3 5 0 8 5 1 5 1 5 0 10 5 High-Z[9] Power-down[10] CE1, CE2, and CE3 LOW to CE1, CE2, or CE3 HIGH to CE1, CE2, or CE3 HIGH to Byte Enable to Data Valid Byte Enable to Low-Z[9] Byte Disable to High-Z[9] 1 5 3 5 3 8 5 1 5 1 8 8 3 10 5 1 10 10 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -10 Max. Unit
CE1, CE2, and CE3 LOW to Power-up[10]
Byte Enable to End of Write
Notes: 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 9. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested.
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CY7C1012AV33
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[4, 14, 15]
ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Write Cycle No. 1 (CE Controlled)[4, 16, 17]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA
Notes: 11. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
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CY7C1012AV33
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[4, 17]
tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tLZWE tHD tPWE tHA
Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied.
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CY7C1012AV33
Truth Table
CE0 H L H H L L H H L L CE1 H H L H L H L H L L CE2 H H H L L H H L L L OE X L L L L X X X X H WE X H H H H L L L L H High-Z I/O0-I/O7 Data Out I/O8-I/O15 Data Out I/O16-I/O23 Data Out Full Data Out I/O0-I/O7 Data In I/O8-I/O15 Data In I/O16-I/O23 Data In Full Data In High-Z I/O0-I/O23 Power-down Read Read Read Read Write Write Write Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 8 10 Ordering Code CY7C1012AV33-8BGC CY7C1012AV33-8BGI CY7C1012AV33-10BGC CY7C1012AV33-10BGI Package Diagram 51-85115 Package Type 119-ball (14 x 22 x 2.4 mm) PBGA Operating Range Commercial Industrial Commercial Industrial
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CY7C1012AV33
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1012AV33
Document History Page
Document Title: CY7C1012AV33 512K x 24 Static RAM Document Number: 38-05254 REV. ** *A *B *C *D *E ECN NO. 113711 117057 117988 118992 120382 492137 Issue Date 03/11/02 07/31/02 09/03/02 09/19/02 11/15/02 See ECN Orig. of Change NSL DFP DFP DFP DFP NXR New Data Sheet Removed 15-ns bin Added 8-ns bin Change Cin - input capacitance -from 6 pF to 8 pF Change Cout -output capacitance from 8 pF to 10 pF Final data sheet. Added note 4 to "AC Test Loads and Waveforms" Removed 12 ns speed bin from product offering Included note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated Ordering Information Table Description of Change
Document #: 38-05254 Rev. *E
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